Traditionally, tuning may have been primarily performed on memory clocks, as in U.S. Pat. No. 6,424,198 granted Jul. 23, 2002 to Wolford, or between chips as in U.S. Pat. No. 5,742,798 granted Apr. 21, 1998 to Goldrian, but on an integrated circuit (IC), tuning clocks has primarily consisted of configuring phase-locked loops (PLLs) or scan clocks, e.g., as presented in U.S. Pat. No. 7,719,315 granted May 18, 2010 to Ngo et al. Recently, in very deep submicron integrated circuit (IC) processes, the metal and semiconductor traces have become so small that the physical structures of their edges may dominate their electrical characteristics. In other words, from chip to chip, the variations in the lithographic processes of the individual wires and vias may vary their resistance and capacitance per unit length by as much as an order of magnitude. While a portion of this variation is a function of design, most of it is a function of fabrication. The variations may occur on a per via, per wire, per manufactured IC basis, regardless of how tight the process parameters are. If all combinatorial logic paths on an IC part were many levels of logic (10 or more), with each level consisting of long wires and large fan-outs, then these per unit length variations may partially average out. Still, for high speed designs, where the critical logic paths consist of 5 or fewer levels of logic, each with short segments and limited fan-out, the variation may be quite large.
In order to improve the performance of such chips, it may be necessary to tune their clocks on a register or even an individual flip-flop basis. This disclosure provides a physical structure and process for fine tuning IC clocks for respective flip-flops, on a chip-by-chip basis.